Affordable Sequence Decoding Techniques for High Speed SerDes

Higher data rate requirements in data centers have motivated more spectrum efficient modulation to combat additional ISI at higher frequencies. But this also leads to significant SNR penalty. In addition to that technology scaling is shifting equalization from analog domain to the digital domain. Therefore, recent trend is to explore ADC-DSP based receiver where higher performance equalization such as viterbi decoder can be implemented. But the power consumption and complexity have limited their adoption in conventional SerDes applications. In this work we will introduce several low power implementation techniques such as analog to sequence conversion and direct branch matric estimation to explore possibility of sequence decoding in SerDes domain. Implemented prototype validates that the proposed sequence decoding is capable of compensating 35+ dB loss at 10 Gb/s with better than 10 pJ/bit energy efficiency.