High LRS-Resistance CMOS Memristive Synapses for Energy-Efficient Neuromorphic SoCs

A gamut of emerging non-volatile memory (NVM) devices, aka memristors, are currently being explored for mixed-signal hardware implementation of artificial neural networks. These constitute vector by matrix multipliers (VMMs) and Neuromorphic computing circuit implementations using NVM crossbar arrays. However, transistor-level circuit designers need to accommodate non-ideal behavior of these devices, that includes variability, low-resistance, finite resolution, relaxation of states, and endurance. In this work, we explore techniques for two-terminal high-LRS (low resistance state) synapses/weights using CMOS-NVM integration that are essential for energy-efficient implementation of Neuromorphic System-on-a-Chip (NeuSoC).