Allocating Gate Reliability for Circuit Reliability Optimization

Reliable operation is increasingly critical for today's digital integrated circuits with nanoscale devices. High reliability requires various considerations and efforts throughout the design flow. However, at gate-level, it could be very time-consuming to conduct circuit reliability analysis and optimization in a global fashion. Currently, a general and computationally practical solution is to do local restructuring and optimization with certain cost constraints, which is less effective. This paper presents a global gate reliability allocation approach to optimize circuit reliability subject to specific cost constraints. With fast reliability estimation based on an asymmetrical reliability model, the proposed method is both effective and efficient with linear-time complexity.