Impact of Time Zero Variability and BTI Reliability on SiNW FET-Based Circuits

In this work, negative bias temperature instability/positive bias temperature instability (NBTI/PBTI) reliability model for p/n-silicon nanowire (SiNW) MOSFETs is obtained from experimental SiNW FETs using a range of stress voltage, time, and temperature. We have incorporated the NBTI/PBTI VT model in a physics-based SiNW FET Verilog-A compact model for circuit analysis. For the first time, using integrated model, we report time zero variability and BTI reliability of the core logic gates (INVERTER, NAND, and NOR) and read/write stability of 6T SRAM cell. We demonstrate that the delay degradation is circuit topology dependent in which series-connected transistors are more prone to degradation due to PBTI (NBTI) in NAND (NOR) gates. The benchmarking of BTI in SiNW FET with FinFET and planar devices show SiNW have higher degradation, however it can be minimized by using optimized SiNW FET configuration. Further, we show that the SRAM cell design margins are configuration dependent in which impact of BTI degrades the read noise margin (RNM) by 15-30%, and write noise margin (WNM) improves by 5-8% for 10-Year lifetime. We find that the combined impact of time zero variability and BTI reliability degrades the mean value of circuit delay and SRAM RNM stability, however, the degradation is found to be comparable to the reported planar and FinFET data. It is also seen that different configuration increases BTI variability (~5-25% increase) which can be minimized. Using the results, we propose a method to minimize degradation under the influence of variability and reliability by selecting appropriate SiNW FET design configuration. The comprehensive predictive model framework presented here is a valuable tool for variability and reliability-aware SiNW CMOS circuit design and analysis.