Design and Analysis of Differentially Graded Double Gated Junctionless Transistors

The scaling of Conventional dynamic random-access memory (DRAM) cell is now in the maximum limit and demands of low-power (LP) consumption for different application. The limitation was overcome by proposing the large number of new device architect. Double Gate MOSFET (DG MOSFET) is one of such device where two gates involving in the control of the Channel. This paper has reported the suitable analysis of Differentially Doped Double Gate MOSFET (DD-DG MOSFET) and the comparison is been done between the Bulk MOSFET and Double Gate MOSFETs. The variation of drain current over the Gate voltage and the Drain voltages in been observed and found better results in case of DD DG MOSFET than UD DG MOSFET.