Timing Synchronization and Viterbi Decoding for FPGA-based SDR Platforms

In this paper we analyze the integration of a digital clock and data recovery with a Viterbi decoder and propose a new interface module that minimizes the detrimental effects of clock jitter on decoded data. The proposed interface avoids decoder idle times and the utilization of a faster clock, optimizing the power consumption. A detailed performance analysis shows that jitter effects on decoding data can be practically eliminate with an appropriate design of the proposed interface.