Digital Correlator: A Scalable and Efficient FPGA Implementation for Radar Receivers

Matched filtering (MF) which maximizes the signal-to-noise ratio (SNR) in presence of additive white noise is one of the core tasks of radar systems. Signal processing has shifted from analog to digital domain, and MF needs to be done digitally. In modern radar systems, the use of Field Programmable Gate Arrays (FPGAs) has become common practice for the real-time radar signal processing. Hence, many FPGA based correlator designs have been proposed for MF. The increase in length, bandwidth and complexity of radar waveforms necessitates efficient and fast correlators with sufficient dynamic range. This paper presents a scalable and efficient fixed point FPGA implementation of a digital correlator which can calculate the periodic cross correlation between the reference and radar return signals in real-time.