Development of Modular Reduction Based on the Divider by Blocking Negative Remainders for Critical Cryptographic Applications

One of the main disadvantage of asymmetric cryptography is its low speed (in comparison with symmetric algorithms). This is very important for critical systems and applications. From this viewpoint in the paper the hardware implementation of a time-critical one of the basic operations of asymmetric cryptosystems-mod reduction is considered. Also an accelerated remainder determination method by an arbitrary modulus of number and the method implementation device based on a divider is proposed. Proposed approach of the negative remainders blocking during division without restoring the remainder is used. The mod reduction device, possessing the raised speed is developed. A step-by-step description of the operation of the device and illustrative examples are provided. The efficiency of the proposed circuit solution is verified on the Artix -7 FPGA from Xilinx for reducible numbers of different digit. Identified and presented in the form of graphs for the dependence of the spent resources of the FPGA Artix-7 on the capacity of the reducible number. Given results can be implemented in critical cryptographic applications for increasing its efficiency.