Abstract:
This letter presents a dc-dc converter realized in a 130-nm CMOS technology that features the same conversion gain as a standard boost converter, but it is able to proces...Show MoreMetadata
Abstract:
This letter presents a dc-dc converter realized in a 130-nm CMOS technology that features the same conversion gain as a standard boost converter, but it is able to process a dual polarity input with a magnitude down to 60 mV. The circuit prototypes feature a regulated output voltage of 1.2 V, an efficiency up to 88% and a maximum output power of 6 mW, while limiting the number of required off-chip components to two capacitors and one inductor.
Published in: IEEE Solid-State Circuits Letters ( Volume: 2, Issue: 9, September 2019)