Bi-Junction Carrier Depletion Type Electro-Optic Phase-Shifters

Summary form only given. Silicon photonic integrated circuits (PICs) combine dense optical system integration with industrial scalability by adopting well-established CMOS fabrication processes [1]. An electro-optic phaseshifter (EOP) represents a basic building unit of several PICs applications [1], including datacom optical switches [3], PIC-FPGAs [4], and beam steering [5]. In-situ resistive-heaters in close vicinity of waveguides [2], or free-carrier injection/depletion in doped junctions [3], are common methods to build EOPs. Literature reports thermal shifters consuming 24.7 mW to achieve DC large signal π-phaseshift [2], power consumption of injection PIN implementations [5] and depletion PN modulators [6] of 10 mW and ≈ 0 mW respectively. A thermal EOP naturally avoids carrier-induced optical insertion losses (IL), in contrast to a PIN/PN modulator. Thus, thermal and PIN/PN methods trade-off IL with electrical power rather than minimizing both [2,3]. An EOP of low optical losses and low electrical power is highly desired in large-signal, and low-speed applications [5, 7]. In this work, we propose a novel low-loss depletion type EOP. The device (Fig. 1A) utilizes a doping cross section, resembling a bi-junction transistor with both junctions reverse biased, in a rib-waveguide. While introducing implants in a waveguide adds IL, their depletion using applied voltage induces phaseshift and decreases IL [3]. Hence, using bi-junctions to increase overlapping area of the optical mode with variable depletion regions, increases induced phaseshift efficiency relative to IL, by minimizing the number of non-depleted implants overlapping with the optical mode. Figure 1B depicts 25 % increase of such overlap in the bi-junction approach relative to a conventional PN modulator under the same implant conditions. Inserting intrinsic regions between central doped area and peripheral ones leverages such higher efficiency to achieve IL of 3 dB less than a conventional NP modulator at a maximum power consumption of 0.3 nW thus preserving desired low power consumption of depletion type modulators and achieving full n-phaseshift at 4.7V. Table 1 lists simulated IL of the proposed devices using Silvaco AtlasTM and Lumerical ModeTM, as well as measurement of a conventional PN junction modulator to verify the model.