Passive SC $\Delta\Sigma$ Modulator Based on Pipelined Charge-Sharing Rotation in 28-nm CMOS

In this paper, we introduce a new switched-capacitor (SC) passive delta-sigma (ΔΣ) modulator architecture. It is based on a charge-sharing rotation technique, which eliminates any inter-stage loading effects that plague the conventional SC passive ΔΣ modulators. To improve the proposed modulator's noise suppression and stability, an independent extra feedback path and a zeroing stage are added to the 2
^nd
-stage integrator. Moreover, a pipelining (i.e. interleaving) technique is employed in the passive low-pass filter to relax settling requirements and improve power efficiency. Compared to the ΔΣ modulators with active integrators, the proposed modulator contains only switches, capacitors and one comparator, thus being greatly amenable to nanoscale CMOS process nodes. Implemented in 28-nm CMOS, the proposed ADC occupies a core area of 0.059 mm
²
. It achieves measured SNDR of 81.1 dB and a measured dynamic range (DR) of 83.6 dB with a signal bandwidth of 80 kHz at 40.96 MS/s, while consuming 101.5 μW. SNDR is maintained above 70 dB across a ±20% supply variation.