Device and Circuit Level Gate Configuration Optimization for 2D Material Field-Effect Transistors

A tied double gate structure has been shown to deliver optimal device-level performance in few-layer MoS2 field-effect transistors. However, the enlarged gate capacitance from the added gate increases circuit-level power consumption and negatively affects minimum obtainable delay. Here, we therefore use a calibrated design-technology co-optimization approach that includes the interconnect load to evaluate back gate size reduction strategies in terms of power and delay. We consider the impact of a spacer region and varying interconnect length. We find that power consumption can be decreased by almost 20% by reducing the back gate overlap with the source-drain contacts without negatively affecting delay, as the carrier injection is occurring dominantly at the contact edges. We also show that opening the back gate underneath the channel provides additional benefit for locally interconnected devices.