High Performance SM2 Elliptic Curve Cryptographic Processor over GF(p)

Elliptic Curve cryptography (ECC) is becoming more and more popular in practice due to their bit size of the operands is much smaller at the same level of security compared to other public-key cryptosystems. The performance of ECC is determined by modular multiplication (MM) and point multiplication (PM). For recommended prime filed, modular multiplication consists of multiplication and fast reduction operations. This paper presents a high performance ECC processor of SM2. A two-stage fast-reduction (TSFR) algorithm over SCA-256 prime field is proposed, which can obtain the result of 0 ≤ Z <; 2ρ instead of 0 ≤ Z <; 14ρ of traditional algorithm. In order to enhance the performance, the operational schedule of PM operation is designed to increase the parallelism of multiplication and fast-reduction operations. Synthesized with a 0.13 um CMOS standard cell library at the frequency of 250MHz, the proposed processor needs 276.54k gates area and PM operation takes 0.057 ms. The processor has make a tradeoff between area and performance, soit is better than other methods.