A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability

This letter presents an energy efficient, temperature-compensated frequency-locked loop (FLL) for use as an on-chip clock source. We first present a fully integrated FLL architecture that significantly improves energy efficiency by using a loop divider to boost the output frequency without requiring increased static power dissipation. We develop models for the FLL energy-per-cycle and temperature stability and use them to implement an energy-optimized and highly temperature-stable FLL design in 65-nm CMOS that achieves 20.3-ppm/°C temperature stability from -20 °C to 60 °C and an energy efficiency of 44.6-fJ/cycle at 23 °C (45.3 nW at 1.016 MHz), which is the highest energy efficiency reported to date for a fully on-chip oscillator, regardless of architecture, operating frequency, or temperature stability.