A Calibration Procedure for Sensor Based Adaptive Voltage Scaling Approaches

Nowadays, VLSI systems suffer from increasing impacts of aging and variability. Traditionally, this is treated by applying extensive guard bands. As those guard bands are chosen at design time, they are necessarily worst case guard bands. Thus, most often they are too pessimistic. Current research tries to mitigate this by means of in-situ performance measurement based Adaptive Voltage Scaling (AVS). AVS typically relies on assumptions regarding the timing behavior of the application logic in relation to the behavior of a specific canary or sensor logic. Most published approaches use manually gained empirical data of just a few test chips and application designs for this purpose. However, to practically apply these techniques, an automatic calibration flow is needed. We propose such an automated calibration flow and test it on multiple FPGAs. We achieve an average power saving of 67%.