Autonomous Scan Patterns for Laser Voltage Imaging

The semiconductor industry ramping up design capabilities for emerging technologies is facing new test quality and yield management challenges. To facilitate debugging of the first silicon, diagnosis of yield issues, and to enable repair processes, an accurate defect isolation is needed with support of advanced test, diagnostic, and yield analysis tools. Laser voltage imaging (LVI), laser voltage probing (LVP), and electron-beam testing are popular diagnostic techniques for scan chain failures. As scan remains instrumental in developing more advanced DFT technologies, its reliable operations are essential for test pattern bring-up, failure analysis, and yield learning. Running LVI tests at early stages of a design process involves a sophisticated infrastructure to offer a nanometer diagnostic resolution with a non-destructive failure isolation. However, as the use of external testers may not be feasible besides providing power and clock signals, the paper demonstrates how to reuse on-chip EDT compression environment to generate and apply LVI-aware scan patterns for advanced contactless test procedures. The presented approach avoids the repetitive loading of scan chains, requires no seed patterns to encode LVI tests, has virtually no area overhead, and offers a flexible selection of non-toggling scan chains in a low power test mode. Furthermore, there are no constraints or requirements imposed by designs that could limit the applicability of the scheme. The proposed solution does not compromise the test compression performance, marked by test data reduction ratios, test coverage, and test time. Hence, there are no modifications needed in existing flows and tools to implement the method besides the use of recommended polynomials.