A New Perspective in Designing an Optimized Fault Tolerant Reversible Multiplier

This paper presents a new approach to design a cost effective fault tolerant reversible multiplier circuit. Unlike existing multiplier circuits that have separate circuits for partial product generation and multi-operand addition, the proposed multiplier, designed using a combination of six distinct blocks, incorporates these two circuits together. It also provides an algorithm that depicts the way of using the blocks in designing a n×n fault tolerant reversible multiplier. The proposed multiplier is simulated to verify the correctness of the design and algorithm. The comparative study shows that the proposed multiplier is more optimized than any existing fault tolerant reversible multiplier in terms of quantum cost, garbage outputs and number of gates used. The proposed multiplier can be used to design a reversible fault tolerant arithmetic logic unit.