Source Underlap—A Novel Technique to Improve Safe Operating Area and Output-Conductance in LDMOS Transistors

In this article, we have proposed a simple, novel, and cost-effective technique to mitigate the ON-state performance issues in laterally diffused MOS (LDMOS) transistors. We propose a novel technique-LDMOS transistor with source-side underlap (SU), which can be integrated into any existing LDMOS/bipolar-CMOS-DMOS (BCD) process flow without any additional processing/area cost. Unlike commonly used solutions, the SU LDMOS provides flexibility to improve ON-state behavior without disturbing other performance metrics. The proposed SU LDMOS transistor is experimentally demonstrated using 180-nm CMOS technology, and noteworthy improvement in ON-state breakdown voltage, electrical safe operating area (SOA), output conductance, transistor intrinsic gain, and cutoff frequency is reported. The physics behind the improvement is also discussed in detail.