Characterization and Modeling of SET Generation Effects in CMOS Standard Logic Cells

Single event transients (SETs) stand out as one of the major causes of soft errors in nanoscale CMOS integrated circuits. To reduce the need for exhaustive circuit simulations in the design of radiation-hard integrated circuits, the cost-effective approaches for characterization and modeling of SET generation effects in standard logic cells are required. In this work, a SPICE-based methodology for characterization of SET generation effects, employing two different SET current models, is presented. Based on the acquired simulation results, the empirical models for the two main SET generation metrics (SET critical charge and SET pulse width) are derived. The SET generation models and the respective model parameters are intended to be used as inputs for the higher-level analysis of SET effects in digital circuits designed with the characterized standard logic cells. By storing the model parameters for each gate in the look-up table, instead of storing the raw data obtained from SPICE simulations, the amount of characterization data can be significantly reduced, allowing to speed up the subsequent SET analysis of a complex circuit.