Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits

Asynchronous circuits are advantageous in various design aspects over their synchronous counterparts. Their FPGA implementation is attractive due to its reconfigurability but challenging due to limited resources. In this work, we craft a library of quasi-delay insensitive (QDI) primitive elements including all functions up to 3-inputs under NPN-equivalence, which are optimized with respect to the target commercial FPGA implementation. We further integrate the library into a synthesis flow. As a case study, we realize an Advanced Encryption Standard (AES) design under our synthesis framework and perform differential power analysis (DPA) to justify the feasibility of our method.