Scribe Line Defect-Induced Yield Loss in FINFET Technology

The scribe line (also known as kerf or frame) is an area in the silicon wafer which is used to separate individual die at the end of wafer processing. The scribe line also contains features which assist in the manufacturing process but are not present in the final product. Examples of such features include lithography alignment and overlay marks, thickness measurement pads, and electrical test macros. The overall design of scribe line features can be drastically different from the die layout. In the chemical mechanical polishing process, regions of low pattern density have higher polishing rates compared to those of high pattern density, leading to overpolishing or “dishing”. The scribe line, with intermittent regions of low and high pattern density, is naturally more prone to dishing, an issue which is exacerbated by thickness variation at the wafer edge. In this work, we present examples of unforeseen defects caused by interaction between process variation and scribe line design, which can eventually lead to yield loss in the prime die. The findings in this paper pertain to “common platform” FINFET technology but can be extended to other technologies due to similar process steps employed in semiconductor manufacturing.