Evaluation of FPGA Based QSPI Flash Access Using Partial Reconfiguration

Field Programmable Gate Arrays (FPGA) based Quad Serial Peripheral Interface (QSPI) Flash Controller becomes popular in embedded system for QSPI flash access. However, as the differences of QSPI flashes available in market are increased drastically, creating a QSPI Flash Controller that can support various QSPI flashes becomes a challenge. Partial Reconfiguration (PR) is introduced to enhance QSPI Flash Controller by implementing each QSPI protocol as a partial reconfigurable module. When a QSPI protocol is needed, the corresponding PR persona is loaded into FPGA. In this paper, FPGA resources required to facilitate PR has no significant difference compared to conventional design. PR able to generate bitstream which is 94% smaller compares to full device bitstream. Thus, PR operation time required to change the QSPI protocol is 61% shorter than time required for full device configuration. The design implementation of single QSPI protocol in a persona is simpler and more scalable.