FPGA Compression Process for Number Theoretic CW Radar With Increased Unambiguous Detection Range

A complete compression-to-detection FPGA design process for a number theoretic CW radar architecture is presented. The architecture uses a unique RSNS (Robust Symmetrical Number System) transform of a P4 polyphase modulation (RSNS-P4) that significantly extends the maximum unambiguous detection range and has an integer Gray code property to minimize detection errors. The FPGA design is both scalable (additional moduli) and reconfigurable and includes a range compression, Doppler signal processor followed by a coherent integration of the range-Doppler maps to provide the correct amount of processing gain required for detection at the unambiguous range. Comparison of the HDL model with the Matlab simulation results with several Swerling-III targets embedded in sea clutter (sea state 2) show excellent agreement.