Complexity Reduction for Multiview HEVC Codec Using FPGA

Due to the increasing quality and resolution of video content, especially 3D video, the computational complexity for its processing also significantly increases. One of the popular format, HEVC has extensions called Multiview HEVC (MV-HEVC) and 3D-HEVC with high amounts of data and high resolution that resulting in increased computational complexity. This study aims to reduce the computational complexity of MV-HEVC videos by implementing mode decision such as ECU, CFM, ESD, and deblocking filters which are tested on Linux-based PC platforms and the Xilinx All Programmable SoC platform. From the experimental results obtained the reduction in computational complexity can be seen from the comparison of encoding time, the Xilinx All Programmable SoC platform is able to obtain encoding times 35.85% that are faster than Linux-based PCs. For the quality of the video produced between the two the platform is not significant from the bitrate and PSNR values.