Heterogeneous System Level Integration Using Active Si Interposer

Achieved system level heterogeneous integration involving 130 nm tech node active Si interposer, two 65 nm tech node I/O chips and one 28 nm tech node FPGA die. Chip on Chip on Substrate packaging methodology was demonstrated for handling active Si interposer die as thin as 40 μm. Different packaging approaches were evaluated and the results are benchmarked. In addition, active Si interposer concept is introduced to provide Analog to Digital Converter (ADC), Digital to Analog Converter (DAC) and Power Management Unit (PMU) functions to support high-performance logic. Furthermore, benefits of active Si approach such as system scaling and cost-effectiveness have been demonstrated. “Via Last” TSV approach is used for the fabrication of 130 nm tech node active Si interposer. It was confirmed that appropriate selection of temporary bonding material plays a critical role in device wafer warpages in via last TSV process flow. Functionality checks were carried out on all samples subjected to preand post-reliability assessments, which include thermal cycling (TC), moisture sensitivity tests (MSL) and highly accelerated stress tests (HAST). All samples were found to be functional with no deterioration in performance despite being subjected to reliability tests and high-voltage stress tests.