Short-Circuit Failure Model of SiC MOSFET Including the Interface Trapped Charges

This article has presented a physics-based model which replicates the failure of SiC MOSFET under short-circuit (SC) case. The model is constructed on the base of the traditional circuit model of SiC MOSFET by introducing two leakage current mechanisms; one is the leakage current between the drain and the source, and another is the gate leakage current. Furthermore, the carrier mobility characterized with trapped charges at the interface of SiC/SiO
₂
is adopted. The failure model had been validated against the experimental results. With the developed failure model, the failure mechanism of SiC MOSFET under a SC event is analyzed; the impact of interface trapped charges on the SC performances of SiC MOSFET is exploited. Moreover, the SC failure for SiC MOSFET with different OFF-state gate voltages has been addressed; the behavior of interface trapped charges has been analyzed.