High Performance and Security Design for Cryptosystem Using Simultaneous Multiple Hardware Threads and Power Aware Technique

Today, cryptography plays an important role for data security and integrity and is widely adopted. The implementation of the cryptography is useful in wireless security like military communication and mobile telephony which have a greater emphasis on the speed of communication, high security and low power consumption. Therefore, we propose a novel architecture for Cryptosystem that enhances the level security and speeds up the data processing using simultaneous multiple hardware threads (SMHT). Moreover, in each hardware thread, we employ two techniques: (1) the pipeline technique to speed up the encryption/decryption data processing; (2) power aware technique to reduce the power consumption. The experimental results show that our proposed architecture not only achieves the high performance for realtime processing of 5.806 Gbps throughput and consumed low-power with 222.75 mW, but also enhances the level of data security. As compared with those founds in the literature, our design was superior in terms of performance, low power consumption and data security.