Design of Hardware Efficient Logarithmic Converter

In this paper a 32-bit binary to binary logarithmic converter for fixed-point (FXP) number system is presented. The error correcting circuit, one of the most important block of this logarithmic converter is designed only using combinational logic. Error correcting circuit used in other logarithmic converter is bit complex than the one implemented in this paper.Both hardware complexity and accuracy are considered while designing various blocks of converter, resulting in fast and more accurate logarithmic conversion.Fast 32-bit Leading one detector circuit is used to obtain the position of leading one from 32-bit binary input. A 32-bit x 5-bit circuit is used to obtain 5-bit integer depending on the corresponding position of leading one.. Also 32-bit Barrel shifter is used to rotate the 32-bit input by 5-bit integer based on output 32-bit x 5-bit circuit. The maximum percentage error is reduced approximately by 17 times due to additional error correcting circuit.