Comparative Performance Analysis of Karatsuba Vedic Multiplier with Butterfly Unit

In DSP processors or other applications which use multiply-accumulate units (MAC) etc., multiplication of large numbers is the main bottleneck. Multiplying two n-bit binary numbers requires n (n - 1 ) adders and n
²
AND gates, which consumes more time, power and area for large n since the hardware scales as the square of n so, there is a need to design a binary multiplier which consumes lesser area, power and delay but in general there will be tradeoff between area, power and delay. With the shrinking of technology we can slightly compromise with area. This paper proposes an efficient method for signed binary multiplication using Urdhva-Tiryagbhyam technique, Karatsuba algorithm and efficient carry select adder. Urdhva-Tiryagbhyam technique is known for its low delay [8] as it produces partial products at same instant and sums them up. It is best suited when the number of bits in the multiplier and multiplicand are less than 16 [8], [14]. Whereas Karatsuba algorithm is applicable for multiplication of larger number of bits [5]. The proposed multiplier is implemented for a first stage butterfly unit [12] of a radix-2 FFT algorithm. This proposed design is implemented using Verilog HDL and synthesized in both 90 nm and 45 nm technology at multiplier level and in 45nm technology for butterfly unit using cadence RTL compiler and results are compared.