Enhance the Segmentation Principle in Approximate Computing

Exploiting the trade-off between accuracy and hardware cost has a tremendous potential to improve the efficiency of integrated systems. Using this concept, numerous approximate adders have been proposed in the literature. This work generalizes and systematically optimizes an architectural template for approximate adders through the conception of Enhanced Segmentation Principle. The outcome, called optimized lower part constant-OR Feedback adder (OFLOCA). Furthermore, a new architecture of approximate adder is proposed which outperforms the all existing Segmented adders which the architecture called Feedback adder (FbA). Through the proposed template, all approximate adders are enhanced and optimized. For example, a 16-bit OFLOCA approximate adder implemented with precise in the higher-part improves the mean squared error and the mean absolute error by 30% and 11% respectively respect to the previously reported best architecture. Furthermore, the enhanced approximate adders outperform their original existing architectures. For functional verification and prototyping, a Xilinx Virtex-5 FPGA have been utilized. The synthesizable RTLs of all approximate adders in generic form are made open-source.