Dynamic Logic Circuits: Combinational and Sequential Design for Digital ICs

Dynamic CMOS logic circuits or Precharge-Evaluate logic circuits have been widely used in high performance digital processors. Their high speed capability has been exploited in both combinational gates as well as sequencing elements. For combinational gates, use of such clocked logic is neither straightforward nor supported by standard EDA tools used by digital IC designers. Due to this, dynamic logic gates remained in their niche of custom design flow. In this paper, various Precharge-Evaluate circuit styles for high speed combinational design are reviewed. A methodology for using Dual Rail Domino logic with standard EDA tools is discussed and implemented on a floating point divider block. The use of Precharge-Evaluate logic for high speed sequencing elements is also discussed. Different high speed flip-flop circuits have been compared. These flip-flops are supported by EDA tools and are specifically designed for use in standard cell library. The test-circuits for flip-flops are simulated using device models of SCL 180nm CMOS Process.