A High Gain Low Power Operational Amplifier using Class AB Output Stage

This paper presents the design and implementation of a high gain, low power CMOS operational amplifier with high impedance class-AB output stage. By use of cascode based transistor connections the operational amplifier is capable of handling input common mode voltage levels close to operating power supply voltage. The transistors at the input stage are operated in the near subthreshold region. Every transistor size in the op amp is designed, validated and operated at V
DD
=1.5V. The proposed amplifier circuit employs a class-AB output stage consisting of PMOS and NMOS transistors, which accounts for better performance such as higher gain, lower static power dissipation, increased unity gain frequency, higher values of slew rate and reduced input-referred noise density than a standard cascode amplifier using emitter follower configuration. The main specifications considered are DC gain, slew rate, power dissipation, phase margin, unity gain bandwidth and CMRR. Circuit level analysis of the proposed amplifier stage is simulated using Cadence Virtuoso schematic editor. The op-amp provides a DC gain of 66.4dB and a unity gain bandwidth of 228MHz at 0.5pF. The power dissipation is found to be 74μW, slew rate is 248.2V/μs, CMRR is 116.6dB and area occupied is 0.058mm
²
.