A 0.18-/spl mu/m 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica

A 200-MHz double-data-rate synchronous-DRAM (DDR-SDRAM) was developed. The chip contains a delay-locked loop (DLL) which performs over a wide range of operating conditions. Post-mold-tuning allows precise replica programming. A 200-MHz intra-chip data bus is suitable for DDR operation.