Smart Wire Bond Solutions for SiP and Memory Packages

Memory device market has grown 12% annually in the past five years. NAND and DRAM comprise majority of the package volume within this segment and each of them have an average annual growth rate of 7%. Ultra-thin dies stacked 32 times are making their way into mass production and very long overhang die structures are becoming increasingly prevalent in new package designs. Multi-Chip modules and SiP applications have also witnessed tremendous growth in recent years. Even with the emergence of several competing packaging technologies, wire bonding is by far the most widely used and cost-effective interconnect solution for SiP and memory device packaging. The dominance of wire bonding is maintained not only due its exceptional flexibility and low cost, but also due to new generations of smart processes that have reduced optimization time, improved reliability and ensured higher yield, all of which further contribute to the cost effectiveness. Modern NAND and DRAM packages have very stringent specifications and often have challenges in ball bond, looping and stitch bond formation. Extremely low loops lower than 35μm that have not been used in mass production before, are now desired to further reduce package height. For packages utilizing Stand-off Stitch bonding (SSB), height and flatness of SSB bump requires finer control. The overhanging die structures are prone to varying amounts of deflection during wire bonding, which in turn affects the quality of the bond and its intermetallic growth. Such dies have higher risk of die crack under the normal forces applied during wire bonding. These challenges increase wire bond process optimization time and the risk of part failure. This paper highlights key advancements in wire bond processes to overcome the aforementioned challenges in modern packages. New ultrasonic and bond force control mechanisms are introduced, and ball bond process improvements are demonstrated for both Au and Cu fine-pitch applications. Au wire remains predominant in memory applications and fine Cu wire is the preferred choice in high pin count SiP applications. Finite element analysis (FEA) of an overhang configuration is presented, compared against experimental results and used to develop and improve calibration routines for minimizing die crack and maximizing throughput. New looping processes that can better withstand die compliance and achieve ≤35 μm loop heights are also demonstrated. Bump formation is explored, and results integrated into smart response-based solutions for achieving a flat-topped bump with finer height control for 0.6 mil wire. All of the above developments significantly reduce overall optimization time. Furthermore, new on-bonder process monitoring capabilities are discussed and shown to improve quality controls, paving the way for industry 4.0 in wire bond process capabilities.