Improved Correlation Between Accelerated Board Level Reliability (BLR) Testing and Customer BLR Results Using a Hybrid Closed-Form/Finite Element Methodology

Performing board level reliability (BLR) testing is an industry-standard practice to validate the robustness of semiconductor packaging and provides guidance to the user as to the thermomechanical fatigue lifetime in the field. However, the occurrence of complex loading conditions (triaxiality) during thermal cycling in the actual application can result in significant deviations from expectations, especially when calculating acceleration factors using Coffin-Manson or Darveaux based equations. Attempts to develop more robust acceleration factors have been limited due to a combination of the large scale of electronic systems and the complex loading conditions that can occur during thermal excursions. To address these challenges, a hybrid methodology for reliability assessment of solder joints in complex assemblies was developed. The hybrid methodology is a combination of creep-equivalent finite element modeling and energy-based closed form equations. The finite element modeling (FEM) consists of a coupled linear elastic thermomechanical analysis of the electronic assembly with secant equations to account for creep behavior. Vectorized stress and strain magnitudes, shear and axial, are then extracted from the critical solder joints. Idealized hysteresis loops are used to capture energy dissipation. Time to failure is then determined through closed form energy-based damage models that partition energy dissipation based on the orientation of the stress loading. This approach is computationally efficient and accurately captures system-level effects, such as underfill, mirroring, and housing-board interactions.