Three-Dimensional Integrated Circuit (3D-IC) Package Using Fan-Out Technology

Three-dimensional integrated circuit (3D-IC) and 2.5D IC with Si interposer are regarded as promising candidates to overcome the limitations of Moore's law due to their advantages of lower power consumption, smaller form factor, higher performance, and higher function density. To achieve 3D and 2.5D IC integrations, several key technologies are required, such as through-silicon via (TSV), wafer thinning and handling, as well as wafer/chip bonding. Among the 3D integrated technologies, TSV process technology is well-known for penetrating via hole inside the chip followed by metal filling. However, the mass production of dedicated chips for TSV purpose is not widely seen across the semiconductor market due to high investment cost and low productivity. Secondly, the conventional POP (Package-on-Package) has the potential risk for solder-joint defect caused by CTE mismatch between top package to bottom package, which may result in poor reliability. To solve these problems, we propose a form of stacked package solution based on Fan-Out Package Technology. This has the advantage of implementing a solder-less joint structure by executing die and via stack-up on panel repeatedly, which can simplify the process flow and improve productivity, reliability as well. In this paper, the development of 2-die stacked package using self-developed Artificial Intelligence (AI) chips was reported. The stacked package has a form factor of 6.75×6.75 mm, 0.78 mmt and ball I/O of 78ea, including two AI chips with size of 4.5×4.6 mm. The package was successfully constructed based on advanced fan-out platform technologies such as the stacking of known good dies under panel level, encapsulation and passivation by laminating thick dielectric material of 150 ìm, the technology which is patterning fine pitch arrayed-via on die pad and deep via in fan-out zone at the same time, void-less via filling.