Comprehensive Solution for Micro Bump Coplanarity Control

Chip-on-Wafer-on-Substrate (CoWoS
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) technology is a promising candidate to enable most cutting edge applications. In CoWoS
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architecture, enormous micro-bumps (uBumps) are adopted for interconnecting top-dies and interposer. Comparing to traditional flip chip bump, uBump encounters high risk for die-to-die joint failure (cold joint) due to limited solder volume. To improve die-to-die stacking quality, uBump coplanarity control is crucial. In this paper, a comprehensive solution is proposed for uBump coplanarity optimization. The solution includes "chip scale" and "uBump scale" approaches, which offers the design/process flexibility for customized chip integration. Based on experiment results, more than 30% of uBump coplanarity reduction is determined. The comprehensive solution is proven as a successful path to mitigate cold joint risk and improve system integration quality.