High Density Ultra-Thin Organic Substrates for Advanced Flip Chip Packages

Advanced semiconductor packaging requirements for higher and faster performance in a thinner and smaller form factor continue to grow for mobile, network and consumer devices. While the increase in device input/output (I/O) density is driven by the famous “Moore's Law”, the packaging industry is experiencing opposing trends for more complex packaging solutions while the expected cost targets are moving in a downward direction. Fine line/space is one of the key requirements for high I/O count packages where die-to-die or die-to-memory integration is needed. Si based inorganic interposers have typically been used in this area for the last few years. However, Si interposers are expensive and supply chain issues can be a serious bottleneck. Although there are few organic interposer solutions in the market, none of these solutions addressed clearly the entire needs of flip chip packages. Demand for high-speed flip chip packages creates an opportunity for highly integrated, multi-chip modules (MCM's) and 2.5D/3D silicon (Si) interposer packages. These packages are emerging very slowly due to the higher costs often associated with infrastructure and supply chain challenges that can happen before a technology is mature. Achieving both increased margins in the power delivery and increased functionality in next generation high-speed applications requires extremely efficient, low loss package designs with an ultra-thin core or coreless substrate with fine line and space. As the substrate gets thinner, it becomes very flexible and one of the biggest assembly challenges for ultra-thin coreless substrates is to keep the substrate flat during the assembly process while still maintaining yield targets. Other issues with thin substrates are related to post assembly such as handling, long-term package reliability and functionality in the application field. The work presented in this paper describes key factors for mitigating several assemblies related issues in the manufacturing line, including package warpage/coplanarity, and selecting the optimum processes and materials for the ultra-thin coreless substrate, called uFOS (Ultra Format Organic Substrate), for flip chip packages with high assembly yields and lower cost. uFOS potential application spaces including die-todie and package-to-package using 2.5D or 2.1D (embedded high-density film or eHDF) methods will be explored using an ultra-thin coreless substrate as an interposer, as opposed to the traditional Si interposer. Various pros and cons along with relative cost data will be discussed. Several design of experiments (DOE) for ultra-thin substrates are being carried out to achieve the objective of the work. Multiple test vehicles have been designed using a flip chip package with an ultra-thin coreless buildup substrate utilizing various assembly materials and processes. The detailed process and some reliability data will be published. More work will be carried out to expand the scope of the technology for multi-chip module (MCM) die and 2.5D integration. Some initial eHDF data will be published as well.