Implementing Logic Functions Using Independently-Controlled Gate in Double-Gate Tunnel FETs: Investigation and Analysis

Recently, a compact realization of logic gates using double-gate tunnel field effect transistors (DGTFETs) with independently-controlled gate has been proposed. The key elements in the proposed implementation are the suppression of the tunneling at the surface using gate-source overlap and enable tunneling inside the TFET body by choosing appropriate silicon body thickness. Though these implementations are compact, our study reveals that there are a few critical problems: high average subthreshold swing (SS
_avg
), low ON-state current (I
_ON
) and large propagation delay (t
_pd
). In this paper, we examine the root cause of these problems and explore solutions to tackle them. It is demonstrated that the techniques that boost the I
_ON
in a TFET do not necessarily increase the I
_ON
/I
_OFF
ratio in the proposed implementations. The efficacy of these techniques in improving the I
_ON
/I
_OFF
ratio depends on whether the gate-source overlap is able to suppress the tunneling at the surface and restrict the OFF-state current (IOFF). Furthermore, it is demonstrated that, for the AND functionality, compared to a purely silicon-based DGTFET (Si-TFET) employing silicongermanium heterojunction DGTFET (HJ-TFET) results in an increase in the I
_ON
by 143×, an increase in the I
_ON
/I
_OFF
ratio by two orders of magnitude and an improvement in the SS
_avg
by 45%, at V
_DD
= 0.6 V. Moreover, a compact NAND gate realized using the proposed HJ-TFETs exhibits two orders of magnitude lower tpd, compared to the NAND gate realized using Si-TFET.