Wafer-Scale Self-Aligned Fabrication of Nanometric Curved Tunneling Junctions

This paper introduces a new self-aligned procedure for wafer-scale fabrication of curved metal-insulator-semiconductor (cMIS) tunneling junctions with nanometric lateral dimensions. The fabrication process is based on the use of an array of silicon nano-pillars embedded in a silicon nitride membrane. The junctions are formed at the apex of pyramidal pits and the tunneling window is defined using self-aligned corner lithography. The current densities of the functional cMIS-junctions with a 2.5 nm thick tunneling oxide layer are in the theoretically expected range.