Soft-Event-Upset and Soft-Event-Transient Tolerant CMOS Circuit Design for Low-Voltage Low-Power Wireless IoT Applications

In the wireless IoT applications, low power is a critical criteria, and low-voltage is a direct way to meet such demand. However, low-voltage criteria in advanced CMOS VLSI designs will lead to critical design challenges in dealing with soft-error interference, especial while the cascade transistor number is limited under low-voltage operations. Some possible low-voltage SEU-tolerant and SET-tolerant circuit design methods are discussed in this paper, such as robust C-element, Error-Correction with Duplication, dual interlocked storage cell (DICE) latch, and such as feedback redundant SEU-tolerant (FERST) latch designs.