Cell Array Design with Row-Driven Source Line in Block Shunt Architecture Applicable to Future 6F2 1T1MTJ Memory

In this paper, we propose a new 1T1MTJ cell array architecture with SL parallel to WL to achieve a small cell size, in which page mode write can be realized without performance degradation. We propose a row-driven source line (RSL) 1T1MTJ memory cell array architecture for minimizing the cell size and a corresponding operational waveform. A block shunt architecture (BSA) that shunts lower source line (LSL) and upper source line (USL) is proposed to make page mode write possible. Size of 1T1MTJ cell can be shrunk to 6F2 when the state-of-the-art design rules are applied.