Twin-Bit Resistive Random Access Memory in FinFET CMOS Logic Technologies

In this paper, a Twin Bit FinFET RRAM fully compatible to advanced FinFET CMOS logic process technology is proposed. Through the new array arrangement and an operation scheme, the set and reset voltage can be effectively separated. In addition, the number of pulses needed to complete a set and reset operation in cycling tests is significantly less than that found in single-bit RRAM cell. Two bits in one cell can be independently set/reset/read without disturbing the other side. Cycling endurance over 10K and data stability in addition to its excellent read/set/reset disturb immunity are demonstrated.