A Programmable Hyper-Dimensional Processor Architecture for Human-Centric IoT

Hyper-dimensional Computing (HDC), a bio-inspired paradigm defined on random high-dimensional vectors, has emerged as a promising IoT paradigm. It is known to provide competitive accuracy on sequential prediction tasks with much smaller model size and training time compared to conventional ML, and is well-suited for human-centric IoT. In the post-Moore scaling era, where increasing variability has challenged traditional designers, its novel computing method based on randomness can be leveraged for continued performance. This work develops a complete, programmable architecture for ultra energy-efficient supervised classification using HD computing. Its simple construction follows from basic HD operations and its massively parallel, shallow datapath (<; 10 logic layers) resembles in-memory computing. The architecture also supports scalability: multiple such processors can be connected pralallely to increase effective HD dimension. A broad evaluation is performed by comparing HDC and 3 conventional ML algorithms on conventional architectures such as CPU and eGPU for instruction count, energy cost and memory requirements. Finally, a 2048-dim ASIC design is synthesized in a 28nm HK/MG process and benchmarked on 9 supervised classification tasks with varying complexity (such as language recognition and human face detection). The simulated chip exhibits energy efficiency <; 1.5μJ/pred. for the entire benchmark at about 2.5ns cycle time, with most applications requiring <; 700 nJ/pred. As a first complete design working with high dimensional stochastic signals, the main architectural decisions for similar systems harnessing variability in emerging devices (eg. CNFET and RRAM) are established. A fabricated system could be readily deployed for human-centric IoT applications.