PEEC Method and Hierarchical Approach Towards 3D Multichip Power Module (MCPM) Layout Optimization

Recent advances in packaging technologies have improved multichip power module (MCPM) power density through innovative designs with layout size reduction, multi-layer stacking, and heterogeneous components integration. As these layout designs are getting denser, signal integrity issues due to mutual couplings demand more consideration. Hence, in order to handle these new layouts in the power module design automation tool-PowerSynth, a new electrical model has been developed based on the PEEC method. This method provides further insights into electrical reliability during optimization by evaluating current density and electric field inside each conductor. A coarse meshing process is applied to every generated layout to ensure accurate parasitic extraction while maintaining efficient computation time. Furthermore, a hierarchical approach has been applied to form connections between traces and components during placement to evaluate electrical parasitics without increasing the number of mesh points. Comparisons versus FEA simulation tools and experiments have shown promising initial extraction results using this model.