Row Hammering Mitigation Using Metal Nanowire in Saddle Fin DRAM

In this article, we investigate a novel technique to minimize row hammer (RH) fail in the saddle fin recessed channel access transistor (S-RCAT) at 1X dynamic random access memory node. We propose a selective introduction of a low work function (WF) metal nanowire (MNW) at the gate metal/gate oxide (GOX) interface to mitigate the RH fail. Using 3-D TCAD simulations, we analyze the mechanism of the RH fail and its mitigation through the use of MNW. The improvement in RH fail is shown due to the MNW and gate-metal workfunction-difference induced energy valleys (EVs) between the neighboring S-RCATs. These valleys prevent the diffusion of electrons from aggressor (accessed) to victim (not accessed) cell, which improves RH fail even in the presence of a high concentration of interface states and gateinduced-drain leakage. The introduction of MNW is found not to have any substantial effect on S-RCAT characteristics (VT, ION, or SS). Furthermore, we model the induced EV by considering the WF difference between MNW and gate metal as an effective charge. This model is shown to be in good agreement with the TCAD results. The results obtained in this study demonstrate the potential of using MNW in the gate-stack of S-RCAT for the elimination of RH fail in 1X technology nodes. This technique can also be extended for the use in other device technologies, such as NAND (cellto-cell interference) and logic transistors.