Logic gates placement algorithm for visualization of integrated circuits netlists

There are still a lot of tasks in IC design which are in need of a program to present text description of a circuit in graphical way. The specific of drawing schematics is the reason why standard algorithms for graph visualization are not applicable to draw circuit graph. This article presents a rank based circuit graph visualization algorithm for displaying combinational digital netlists. It allows to visualize netlist graph of a given flat transistor level netlist or gate netlist of a circuit in correct way according to generally accepted rules for the elements placement.