Model of the Yield Loss Factors Based on Survey Analysis for the Integrated Circuits Manufacturing

The effective decision of continuous increase of technological level and the economic efficiency of semiconductor manufacturing demands the adequate statistical models describing distribution of defects and yield. In the paper, motivated by semiconductor manufacturing, we study a problem of data association of condition of technological process. This work presents a yield analysis method using basic operating defect information to statistically define essential original causes of yield loss in semiconductor manufacturing. Using simple statistics on yield loss percent, this method provides the process list on influence of yield loss. This tool is also applied to selection of the most effective inspection tool. Complete understanding of the inspection equipment is not required for its statement. Analysis by sizes and types of defects provides decision and elimination of defects. The paper aspires to offer the model of yield loss percent distributions in semiconductor manufacturing based on estimations of operator-technologists directly in the IC manufacturing. A wide range of alternative modeling approaches has been carried out up to now. Also the large variety of criteria and tests has been used to estimate of the forecast accuracy on various volume of dataset. Results offer a robust comparative tools if we have a full source of the information for process. The described method could be especially useful tool for the persons making decision. Besides, models allow to receive valuable forecasts for turning points when various improvements implemented into technological process. It allows to predict somewhat result of process and to catch a trend. This model may be extended for the yield forecasting using a similar approach.