Suppression of Harmonics and Instabilities of Single-Phase Inverters Caused by Delay-based Phase-Locked Loop in the Weak Grid

Phase-locked loops (PLLs) are the key technique for inverters to be synchronized with the PCC voltage. Typically, in the single-phase applications, the delay-based PLL is being widely used. However, for nowadays applications where the inverter may be connected to the PCC with large grid impedance, the inverter performance can be endangered, and harmonics or even instabilities are aroused. Although there are some relevant literatures, the solutions for solving the adverse impacts of delay-PLL on the system performance are still not well documented. Therefore, this paper aims to study the limitations of delay-based PLL and provide an improved approach. Through the inverter output impedance modelling, the reason why the delay-based PLL causes the instability in the weak grid case has been clearly explained. Then, the way to solve the instability caused by the PLL has been discussed, and an improved delay-based PLL has been proposed to improve the weak grid compatibility of inverters. The single-phase inverter system can then work well when the grid impedance varies widely.