Charge-Based Model for Reliability Analysis Flow of Flip- Flops under Process Variation and Aging

This paper analyzes the combined effects of process variation and aging, namely HCI and BTI, on the performance of flip-flops. To enable this evaluation, a stochastic reliability simulation flow which combines Monte Carlo simulations with degradation is presented. It makes use of a charged-based degradation-aware transistor model incorporating both process variation and aging effects into a normal SPICE simulation without the need of an additional aging simulator. The simulation flow enables the continuous evaluation of the changing stress conditions while keeping the simulation effort at a reasonable level. The analysis is performed on two different flip-flop architectures, a master slave flip-flop and a pulsed flip-flop, to determine the shift of timing performance distributions over time as well as the dependence on temperature.